Idleness-aware dynamic power mode selection on the i.Mx 7ULP iot edge processor

Power management is a crucial concern in micro-controller platforms for the Internet of Things (IoT) edge. Many applications present a variable and difficult to predict workload profile, usually driven by external inputs. The dynamic tuning of power consumption to the application requirements is indeed a viable approach to save energy. In this paper, we propose the implementation of a power management strategy for a novel low-cost low-power heterogeneous dual-core SoC for IoT edge fabricated in 28 nm FD-SOI technology. Ss with more complex power management policies implemented on high-end application processors, we propose a power management strategy where the power mode is dynamically selected to ensure user-specified target idleness. We demonstrate that the dynamic power mode selection introduced by our power manager allows achieving more than 43% power consumption reduction with respect to static worst-case power mode selection, without any significant penalty in the performance of a running application

A forward body bias generator for digital CMOS circuits with supply voltage scaling

We propose a new fully-integrated forward body bias (FBB) generator that holds its voltage constant relative to the (scalable) power supply of a digital IP. The generator is modular and can drive distinct digital IP block sizes in multiples of up to 1mm2. The design has been implemented in 90nm low-power CMOS. Our basic unit for driving digital IP blocks up to 1mm2 occupies a silicon area of 0.03mm2 only. The generator completes a 500mV FBB voltage step within 4µs. The bandwidth of the design is 570kHz. The active current of the FBB generator alone is about 177µA for a nominal process, 1.2V supply and 85°C. The standby current is as low as 72nA at 27°C

Prelayout interconnect yield prediction

Functional yield is a term used to describe the percentage of dies on a wafer that are not affected by catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires and cuts, which result in broken wires. Functional yield is therefore determined by the geometry of the routing channels, how these channels are filled with wire and the distribution of defect sizes. Since the wire spacing and width are usually fixed and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Previous work in this area has analyzed the problem by assuming that all wiring tracks are occupied with wire, leading to overestimates for the probability of failure due to both cuts and bridges. This paper utilizes statistical models of the placement/routing process to provide a more realistic approach for cut and bridge yield estimation. A comparison of the predicted probability of failure within each wiring layer with postlayout data indicate an average error of 20% for cuts and 26% for bridges

Pre-layout prediction of interconnect manufacturability

Functional yield is a term used to describe the percentage of dies on a wafer that fail due to catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires, and cuts, which result in broken wires. The probability of failure is therefore determined by the geometry of the routing channels and the distribution of defect sizes. Since the wire spacing and width are usually fixed, and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts, and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Since the probability of failure is determined by the behavior of the wires averaged over the entire interconnect, the application of System Level Interconnect Prediction (SLIP) techniques is particularly appropriate. This paper presents a method for utilizing previously developed techniques for wire length estimation and layer assignment and applies them to the problem of cut and bridge functional yield estimation

Prelayout interconnect yield prediction

Functional yield is a term used to describe the percentage of dies on a wafer that are not affected by catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires and cuts, which result in broken wires. Functional yield is therefore determined by the geometry of the routing channels, how these channels are filled with wire and the distribution of defect sizes. Since the wire spacing and width are usually fixed and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Previous work in this area has analyzed the problem by assuming that all wiring tracks are occupied with wire, leading to overestimates for the probability of failure due to both cuts and bridges. This paper utilizes statistical models of the placement/routing process to provide a more realistic approach for cut and bridge yield estimation. A comparison of the predicted probability of failure within each wiring layer with postlayout data indicate an average error of 20% for cuts and 26% for bridges

Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCs

The recent growth of applications in the emerging Internet of Things field is posing new challenges in the longterm deployments of sensing devices. Currently, system designers rely on energy harvesting to reduce battery size and extend system lifetime. While some system functions need constant power supply, others can have their service adapted dynamically to available harvested energy. In this work we propose Torpor, a power-aware HW scheduler which continuously monitors harvesting power and in combination with its software runtime, dynamically activates system functions depending on the available energy. By performing a few key functions in HW, Torpor incurs a very low power overhead during continuous monitoring, while the software runtime provides a high degree of flexibility to enable different scheduling policies. We implemented Torpor on a FPGA-based prototype and demonstrated that with a sample power-aware dynamic scheduling policy, we can have a 2 7 or more improvement in execution rates compared to static (power-ignorant) policies. The power consumption of Torpor's always-on hardware integrated on chip is estimated to be less than 4 \u3bcW, making it a very promising power-management add-on for microprocessors used in IoT nodes

Energy and power awareness in hardware schedulers for energy harvesting IoT SoCs

The recent growth of applications in the emerging Internet of Things field is posing new challenges in the long-term deployments of sensing devices. Currently, system designers rely on energy harvesting to reduce battery size and extend system lifetime. While some system functions need constant power supply, others can have their service adapted dynamically to the available harvested energy and harvesting power. Our proposed Torpor is a power-aware hardware scheduler which continuously monitors harvesting power and in combination with its software runtime, dynamically activates system functions depending on the available energy and its rate of change. By performing a few key functions in hardware, Torpor incurs a very low power overhead during continuous monitoring, while the software runtime provides a high degree of flexibility to enable different scheduling policies. We implemented Torpor on a FPGA-based prototype and demonstrated that dynamic scheduling policies which take the harvesting power into account can have a 2 7 or more improvement in execution rates compared to static (input-power-independent) policies, while dynamic policies that are aware also of the system's power consumption can achieve 1.5 7 improvement in the execution rates compared to the ones that do not. The power consumption of Torpor's always-on hardware integrated on chip is estimated to be less than 4 \u3bcW, making it a very promising power-management add-on for microprocessors used in IoT nodes